The present disclosure relates to multilayer semiconductor devices in which packages enclosing semiconductor chips are stacked and connected together.
In recent years, with progress in miniaturization and an increase in functions of information and communication equipments and office electronic equipments, miniaturization and an increase in the number of external terminals for input and output are required in semiconductor devices mounted in such equipments and including semiconductor integrated circuit devices etc. However, in a system in which a plurality of semiconductor devices are mounted on a same plane, semiconductor devices for mobile equipments particularly requiring miniaturization and a decease in thicknesses are difficult to manufacture.
As a technique for meeting such requirements, package-on-package (PoP) structures have been increasingly used, which are multilayer package structures with high integration. A conventional semiconductor device will be described below with reference to FIG. 3.
FIG. 3 is a cross-sectional view illustrating a conventional multilayer semiconductor device having a PoP structure. As shown in the figure, metal bumps 102, which are made of solder, and are mechanically and electrically connected to electrode terminals on a semiconductor chip 101, are formed on the semiconductor chip 101. The semiconductor chip 101 is flip-chip mounted on an interconnect substrate 103 with the metal bumps 102 interposed therebetween, and is mechanically and electrically connected to the interconnect substrate 103. Underfill resin 106 for encapsulating the metal bumps 102 fills a space between the semiconductor chip 101 and the interconnect substrate 103. External connection terminals 107 made of solder are formed on a surface (hereinafter referred to as a “bottom surface”) of the interconnect substrate 103 opposite to a semiconductor chip mounting surface (hereinafter referred to as a “top surface”). Connection terminals 104 are arranged in regions in the top surface of the interconnect substrate 103, on which the semiconductor chip 101 is not mounted and which surround the semiconductor chip 101 when viewed from above. As such, a lower package is formed. A multilayer package 108 including electrode lands 109 on the bottom surface is mechanically and electrically connected to the top of the lower package via metal balls 110 made of solder. The metal balls 110 mechanically and electrically connect the connection terminals 104 to the electrode lands 109, and are electrically connected to the external connection terminals 107.
A method of manufacturing the flip-chip mounted multilayer semiconductor device will be described below.
First, the semiconductor chip 101, on which the metal bumps 102 are formed by electroplating, printing, ball mounting, etc., and the interconnect substrate 103, in which electrode lands are formed in positions corresponding to the metal bumps 102, are prepared. Then, the semiconductor chip 101 is flip-chip connected to the top of the interconnect substrate 103.
Next, the solder is melted by reflowing the metal bumps 102 of the semiconductor chip 101 so that the semiconductor chip 101 is connected to the interconnect substrate 103 by the metal bumps 102.
After that, the space between the semiconductor chip 101 and the interconnect substrate 103 is cleaned, and the underfill resin 106 is injected into the space with a dispenser. The resin is injected from a periphery of the semiconductor chip 101. The liquid resin enters the entire space between the semiconductor chip 101 and the interconnect substrate 103 due to capillary action so that the underfill resin 106 fills the space between the semiconductor chip 101 and the interconnect substrate 103.
Then, heat treatment is performed to cure the underfill resin 106, thereby encapsulating a circuit formation surface of the semiconductor chip 101 and the portions connected by the metal bumps 102.
Finally, the external connection terminals 107 are formed on metal pads extracted to the surface (bottom surface) of the interconnect substrate 103 opposite to the top surface (chip mounting surface), and then reflow is performed.
As such, a ball grid array (BGA) multilayer semiconductor device is completed.